Field of the Invention
The present invention relates to an improved MNOS transistor employed in non-volatile memory devices.
State of the Prior Art
In the past, the metal-nitride-oxide-silicon (MNOS) structure has been employed in non-volatile charge-storage memory arrays. The MNOS structure was generally configured in the form of a transistor with source and drain terminals and a single memory gate for "current accessing" the stored charge. The stored charge determined the threshold voltage of the transistor, which in turn, affected the magnitude of the current flow between the source and drain terminals for specified read voltage on the memory gate electrode. In attempting miniaturization, it was found that as the prior art MNOS structure was reduced in size, such factors as read disturb effect, and speed were detrimentally affected.